<\/p>\n
![\"A](\"https:\/\/www.hceics.com\/wp-content\/uploads\/mi-v-Microchip_overview.jpg\")
<\/p>\n
A high-level overview of Microchip’s Mi-V ecosystem. Image used courtesy of\u00a0Microchip<\/a><\/em><\/h5>\n <\/p>\n
In this article, we\u2019ll look at the reasons for pairing RISC-V and\u00a0FPGAs<\/a>, the\u00a0PolarFire SoC FPGA<\/a>, and the Mi-V Ecosystem.<\/p>\n <\/p>\n
Blending FPGAs and RISC-V<\/h3>\n
One of Microchip\u2019s crowning achievements in the RISC-V world has been its PolarFire SoC, a piece of hardware that builds a RISC-V system out of FPGA fabric. Naturally, this raises the question: why blend FPGAs and RISC-V together?<\/p>\n
An answer to this question is that RISC-V and FPGAs are both designed to do a similar thing\u2014provide users with flexibility and customization. FPGAs are software-defined hardware, meaning users can write specialized hardware description language (HDL) code to shape their FPGA fabric into custom computing blocks and hardware accelerators.<\/p>\n
<\/p>\n
![\"An](\"https:\/\/www.hceics.com\/wp-content\/uploads\/RISC-V_block_diagram.png\")
<\/p>\n
An example block diagram with a blend of RISC-V and FPGA. Image used courtesy of\u00a0Microchip<\/a><\/em><\/h5>\n <\/p>\n
By the same token, RISC-V was developed to make hardware design and customization accessible to everyone.<\/p>\n
In this way, the merger between FPGAs and RISC-V can make perfect sense. The combination affords designers a highly customizable, open-source platform to rapidly iterate, customize, and optimize their designs for their intended use cases.<\/p>\n
<\/p>\n
PolarFire SoC FPGA<\/h3>\n
Microchip made headlines in the RISC-V world this week when it announced that its PolarFire SoC FPGA had entered mass production.<\/p>\n
As AAC contributor\u00a0Lisa Boneta previously described<\/a>, Microchip\u2019s PolarFire SoC is a RISC-V-based SoC built entirely on FPGA fabric. The system consists of a RISC-V microprocessor subsystem in hardened FPGA logic, coupled with the PolarFire FPGA portion of the SoC. The highlights of the hardened microprocessor subsystem consist of a system controller, a RISC-V monitor core, a quad-core RISC-V application cluster, and a deterministic L2 memory subsystem. On the FPGA side, the SoC features up to 460K logic elements, 12.7 Gbps transceivers, and PCIe 2 I\/O.<\/p>\n <\/p>\n
![\"PolarFire](\"https:\/\/www.hceics.com\/wp-content\/uploads\/polarfire_soc_block_diagram_1.jpg\")
<\/a><\/p>\nPolarFire SoC block diagram. Image used courtesy of\u00a0Microchip<\/a>\u00a0[click to enlarge]<\/em><\/h5>\n <\/p>\n
Altogether Microchip lauds the PolarFire SoC, claiming it delivers up to 50% lower power than comparable FPGAs. The company quantifies this, by stating that at 1.3 W, the PolarFire SoC can deliver up to 6500 CoreMarks as opposed and consumes 55% lower power at 8000 CoreMarks than competitors.<\/p>\n
<\/p>\n
Mi-V Ecosystem<\/h3>\n
Along with the mass production of the PolarFire SoC, Microchip has also announced continual support of its Mi-V Ecosystem.<\/p>\n
<\/p>\n
Blending FPGAs and RISC-V<\/h3>\n
One of Microchip\u2019s crowning achievements in the RISC-V world has been its PolarFire SoC, a piece of hardware that builds a RISC-V system out of FPGA fabric. Naturally, this raises the question: why blend FPGAs and RISC-V together?<\/p>\n
An answer to this question is that RISC-V and FPGAs are both designed to do a similar thing\u2014provide users with flexibility and customization. FPGAs are software-defined hardware, meaning users can write specialized hardware description language (HDL) code to shape their FPGA fabric into custom computing blocks and hardware accelerators.<\/p>\n
<\/p>\n
<\/p>\n
An example block diagram with a blend of RISC-V and FPGA. Image used courtesy of\u00a0Microchip<\/a><\/em><\/h5>\n <\/p>\n
By the same token, RISC-V was developed to make hardware design and customization accessible to everyone.<\/p>\n
In this way, the merger between FPGAs and RISC-V can make perfect sense. The combination affords designers a highly customizable, open-source platform to rapidly iterate, customize, and optimize their designs for their intended use cases.<\/p>\n
<\/p>\n
PolarFire SoC FPGA<\/h3>\n
Microchip made headlines in the RISC-V world this week when it announced that its PolarFire SoC FPGA had entered mass production.<\/p>\n
As AAC contributor\u00a0Lisa Boneta previously described<\/a>, Microchip\u2019s PolarFire SoC is a RISC-V-based SoC built entirely on FPGA fabric. The system consists of a RISC-V microprocessor subsystem in hardened FPGA logic, coupled with the PolarFire FPGA portion of the SoC. The highlights of the hardened microprocessor subsystem consist of a system controller, a RISC-V monitor core, a quad-core RISC-V application cluster, and a deterministic L2 memory subsystem. On the FPGA side, the SoC features up to 460K logic elements, 12.7 Gbps transceivers, and PCIe 2 I\/O.<\/p>\n <\/p>\n
<\/a><\/p>\nPolarFire SoC block diagram. Image used courtesy of\u00a0Microchip<\/a>\u00a0[click to enlarge]<\/em><\/h5>\n <\/p>\n
Altogether Microchip lauds the PolarFire SoC, claiming it delivers up to 50% lower power than comparable FPGAs. The company quantifies this, by stating that at 1.3 W, the PolarFire SoC can deliver up to 6500 CoreMarks as opposed and consumes 55% lower power at 8000 CoreMarks than competitors.<\/p>\n
<\/p>\n
Mi-V Ecosystem<\/h3>\n
Along with the mass production of the PolarFire SoC, Microchip has also announced continual support of its Mi-V Ecosystem.<\/p>\n
<\/p>\n
<\/p>\n Altogether Microchip lauds the PolarFire SoC, claiming it delivers up to 50% lower power than comparable FPGAs. The company quantifies this, by stating that at 1.3 W, the PolarFire SoC can deliver up to 6500 CoreMarks as opposed and consumes 55% lower power at 8000 CoreMarks than competitors.<\/p>\n <\/p>\n Along with the mass production of the PolarFire SoC, Microchip has also announced continual support of its Mi-V Ecosystem.<\/p>\n<\/a><\/p>\nPolarFire SoC block diagram. Image used courtesy of\u00a0Microchip<\/a>\u00a0[click to enlarge]<\/em><\/h5>\n
Mi-V Ecosystem<\/h3>\n